This source file includes following definitions.
- opal_atomic_mb
- opal_atomic_rmb
- opal_atomic_wmb
- opal_atomic_isync
- opal_atomic_compare_exchange_strong_32
- opal_atomic_compare_exchange_strong_acq_32
- opal_atomic_compare_exchange_strong_rel_32
- opal_atomic_compare_exchange_strong_64
- opal_atomic_compare_exchange_strong_acq_64
- opal_atomic_compare_exchange_strong_rel_64
- opal_atomic_fetch_add_32
- opal_atomic_fetch_sub_32
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34 #ifndef OPAL_SYS_ARCH_ATOMIC_H
35 #define OPAL_SYS_ARCH_ATOMIC_H 1
36
37 #if (OPAL_ASM_ARM_VERSION >= 7)
38
39 #define OPAL_HAVE_ATOMIC_MEM_BARRIER 1
40
41
42 #define MB() __asm__ __volatile__ ("dmb" : : : "memory")
43 #define RMB() __asm__ __volatile__ ("dmb" : : : "memory")
44 #define WMB() __asm__ __volatile__ ("dmb" : : : "memory")
45
46 #elif (OPAL_ASM_ARM_VERSION == 6)
47
48 #define OPAL_HAVE_ATOMIC_MEM_BARRIER 1
49
50
51 #define MB() __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 5" : : : "memory")
52 #define RMB() MB()
53 #define WMB() MB()
54
55 #else
56
57 #define OPAL_HAVE_ATOMIC_MEM_BARRIER 1
58
59
60 #define MB() (*((void (*)(void))(0xffff0fa0)))()
61 #define RMB() MB()
62 #define WMB() MB()
63
64 #endif
65
66
67
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70
71
72 #if (OPAL_HAVE_ATOMIC_MEM_BARRIER == 1)
73
74 static inline
75 void opal_atomic_mb(void)
76 {
77 MB();
78 }
79
80
81 static inline
82 void opal_atomic_rmb(void)
83 {
84 RMB();
85 }
86
87
88 static inline
89 void opal_atomic_wmb(void)
90 {
91 WMB();
92 }
93
94 static inline
95 void opal_atomic_isync(void)
96 {
97 }
98
99 #endif
100
101
102
103
104
105
106
107
108 #if (OPAL_GCC_INLINE_ASSEMBLY && (OPAL_ASM_ARM_VERSION >= 6))
109
110 #define OPAL_HAVE_ATOMIC_COMPARE_EXCHANGE_32 1
111 #define OPAL_HAVE_ATOMIC_MATH_32 1
112 static inline bool opal_atomic_compare_exchange_strong_32 (opal_atomic_int32_t *addr, int32_t *oldval, int32_t newval)
113 {
114 int32_t prev, tmp;
115 bool ret;
116
117 __asm__ __volatile__ (
118 "1: ldrex %0, [%2] \n"
119 " cmp %0, %3 \n"
120 " bne 2f \n"
121 " strex %1, %4, [%2] \n"
122 " cmp %1, #0 \n"
123 " bne 1b \n"
124 "2: \n"
125
126 : "=&r" (prev), "=&r" (tmp)
127 : "r" (addr), "r" (*oldval), "r" (newval)
128 : "cc", "memory");
129
130 ret = (prev == *oldval);
131 *oldval = prev;
132 return ret;
133 }
134
135
136
137
138
139
140 static inline bool opal_atomic_compare_exchange_strong_acq_32 (opal_atomic_int32_t *addr, int32_t *oldval, int32_t newval)
141 {
142 bool rc;
143
144 rc = opal_atomic_compare_exchange_strong_32 (addr, oldval, newval);
145 opal_atomic_rmb();
146
147 return rc;
148 }
149
150
151 static inline bool opal_atomic_compare_exchange_strong_rel_32 (opal_atomic_int32_t *addr, int32_t *oldval, int32_t newval)
152 {
153 opal_atomic_wmb();
154 return opal_atomic_compare_exchange_strong_32 (addr, oldval, newval);
155 }
156
157 #if (OPAL_ASM_SUPPORT_64BIT == 1)
158
159 #define OPAL_HAVE_ATOMIC_COMPARE_EXCHANGE_64 1
160 static inline bool opal_atomic_compare_exchange_strong_64 (opal_atomic_int64_t *addr, int64_t *oldval, int64_t newval)
161 {
162 int64_t prev;
163 int tmp;
164 bool ret;
165
166 __asm__ __volatile__ (
167 "1: ldrexd %0, %H0, [%2] \n"
168 " cmp %0, %3 \n"
169 " it eq \n"
170 " cmpeq %H0, %H3 \n"
171 " bne 2f \n"
172 " strexd %1, %4, %H4, [%2] \n"
173 " cmp %1, #0 \n"
174 " bne 1b \n"
175 "2: \n"
176
177 : "=&r" (prev), "=&r" (tmp)
178 : "r" (addr), "r" (*oldval), "r" (newval)
179 : "cc", "memory");
180
181 ret = (prev == *oldval);
182 *oldval = prev;
183 return ret;
184 }
185
186
187
188
189
190
191 static inline bool opal_atomic_compare_exchange_strong_acq_64 (opal_atomic_int64_t *addr, int64_t *oldval, int64_t newval)
192 {
193 bool rc;
194
195 rc = opal_atomic_compare_exchange_strong_64 (addr, oldval, newval);
196 opal_atomic_rmb();
197
198 return rc;
199 }
200
201
202 static inline bool opal_atomic_compare_exchange_strong_rel_64 (opal_atomic_int64_t *addr, int64_t *oldval, int64_t newval)
203 {
204 opal_atomic_wmb();
205 return opal_atomic_compare_exchange_strong_64 (addr, oldval, newval);
206 }
207
208 #endif
209
210
211 #define OPAL_HAVE_ATOMIC_ADD_32 1
212 static inline int32_t opal_atomic_fetch_add_32(opal_atomic_int32_t* v, int inc)
213 {
214 int32_t t, old;
215 int tmp;
216
217 __asm__ __volatile__(
218 "1: ldrex %1, [%3] \n"
219 " add %0, %1, %4 \n"
220 " strex %2, %0, [%3] \n"
221 " cmp %2, #0 \n"
222 " bne 1b \n"
223
224 : "=&r" (t), "=&r" (old), "=&r" (tmp)
225 : "r" (v), "r" (inc)
226 : "cc", "memory");
227
228
229 return old;
230 }
231
232 #define OPAL_HAVE_ATOMIC_SUB_32 1
233 static inline int32_t opal_atomic_fetch_sub_32(opal_atomic_int32_t* v, int dec)
234 {
235 int32_t t, old;
236 int tmp;
237
238 __asm__ __volatile__(
239 "1: ldrex %1, [%3] \n"
240 " sub %0, %1, %4 \n"
241 " strex %2, %0, [%3] \n"
242 " cmp %2, #0 \n"
243 " bne 1b \n"
244
245 : "=&r" (t), "=&r" (old), "=&r" (tmp)
246 : "r" (v), "r" (dec)
247 : "cc", "memory");
248
249 return t;
250 }
251
252 #endif
253
254 #endif