1 /* -*- Mode: C; c-basic-offset:4 ; indent-tabs-mode:nil -*- */
2 /*
3 * Copyright (c) 2004-2005 The Trustees of Indiana University and Indiana
4 * University Research and Technology
5 * Corporation. All rights reserved.
6 * Copyright (c) 2004-2014 The University of Tennessee and The University
7 * of Tennessee Research Foundation. All rights
8 * reserved.
9 * Copyright (c) 2004-2005 High Performance Computing Center Stuttgart,
10 * University of Stuttgart. All rights reserved.
11 * Copyright (c) 2004-2005 The Regents of the University of California.
12 * All rights reserved.
13 * Copyright (c) 2016 Los Alamos National Security, LLC. ALl rights
14 * reserved.
15 * Copyright (c) 2018 Intel, Inc. All rights reserved.
16 * $COPYRIGHT$
17 *
18 * Additional copyrights may follow
19 *
20 * $HEADER$
21 */
22
23 #ifndef PMIX_SYS_ARCH_TIMER_H
24 #define PMIX_SYS_ARCH_TIMER_H 1
25
26
27 typedef uint64_t pmix_timer_t;
28
29 /* Using RDTSC(P) results in non-monotonic timers across cores */
30 #undef PMIX_TIMER_MONOTONIC
31 #define PMIX_TIMER_MONOTONIC 0
32
33 #if PMIX_GCC_INLINE_ASSEMBLY
34
35 /* TODO: add AMD mfence version and dispatch at init */
36 static inline pmix_timer_t
37 pmix_sys_timer_get_cycles(void)
38 {
39 uint32_t l, h;
40 __asm__ __volatile__ ("lfence\n\t"
41 "rdtsc\n\t"
42 : "=a" (l), "=d" (h));
43 return ((pmix_timer_t)l) | (((pmix_timer_t)h) << 32);
44 }
45
46 static inline bool pmix_sys_timer_is_monotonic (void)
47 {
48 int64_t tmp;
49 int32_t cpuid1, cpuid2;
50 const int32_t level = 0x80000007;
51
52 /* cpuid clobbers ebx but it must be restored for -fPIC so save
53 * then restore ebx */
54 __asm__ volatile ("xchg %%rbx, %2\n"
55 "cpuid\n"
56 "xchg %%rbx, %2\n":
57 "=a" (cpuid1), "=d" (cpuid2), "=r" (tmp) :
58 "a" (level) :
59 "ecx", "ebx");
60 /* bit 8 of edx contains the invariant tsc flag */
61 return !!(cpuid2 & (1 << 8));
62 }
63
64 #define PMIX_HAVE_SYS_TIMER_GET_CYCLES 1
65 #define PMIX_HAVE_SYS_TIMER_IS_MONOTONIC 1
66
67 #else
68
69 pmix_timer_t pmix_sys_timer_get_cycles(void);
70
71 #define PMIX_HAVE_SYS_TIMER_GET_CYCLES 1
72
73 #endif /* PMIX_GCC_INLINE_ASSEMBLY */
74
75 #endif /* ! PMIX_SYS_ARCH_TIMER_H */