maxwidth           77 opal/mca/hwloc/hwloc201/hwloc/hwloc/topology-nvml.c 	unsigned maxwidth = 0, maxgen = 0;
maxwidth           79 opal/mca/hwloc/hwloc201/hwloc/hwloc/topology-nvml.c 	nvmlDeviceGetMaxPcieLinkWidth(device, &maxwidth);
maxwidth           86 opal/mca/hwloc/hwloc201/hwloc/hwloc/topology-nvml.c 	if (lanespeed * maxwidth != 0.)
maxwidth           88 opal/mca/hwloc/hwloc201/hwloc/hwloc/topology-nvml.c 	  parent->attr->pcidev.linkspeed = lanespeed * maxwidth / 8; /* GB/s */