Keynote-3: Richard Vuduc (Georgia Institute of Technology, USA)

Speaker: Richard Vuduc (Georgia Institute of Technology, USA)

Title: Performance engineering for sparse matrix, tensor, and graph computations

Date:  – , Thursday, August 8th

Location: Buzz Hall

Chair: Martin Schulz


At the heart of many computational problems in scientific computing and data analysis lie sparse matrix, tensor, and graph computations. This talk summarizes a few of our recent results in the design of communication-avoiding algorithms, data structures, and controller-based dynamic tuning and control software for such computations. Specific examples will include the sparse direct solvers, tensor decompositions, and the calculation of shortest paths in graph analysis. Collectively, this work sheds light on fundamental issues of how to mitigate the high cost of communication, increasing need to improve locality, and operate efficiently in heterogeneous power-constrained environments.

About the Speaker

Richard (Rich) Vuduc is a Professor at the Georgia Institute of Technology (“Georgia Tech”). He works in the School of Computational Science and Engineering, a department devoted to the study of computer-based modeling, simulation, and data-driven analysis of natural and engineered systems. His research lab, The HPC Garage (@hpcgarage), is interested in high-performance computing, with an emphasis on algorithms, performance analysis, and performance engineering. He is a recipient of a DARPA Computer Science Study Group grant; an NSF CAREER award; a collaborative Gordon Bell Prize in 2010; Lockheed-Martin Aeronautics Company Dean’s Award for Teaching Excellence (2013); and Best Paper or Best Student Paper Awards at the SIAM Conference on Data Mining (SDM, 2012), the IEEE Parallel and Distributed Processing Symposium (IPDPS, 2015), and the ACM/IEEE Conference on Supercomputing (SC, 2018), among others. He has also served as his department’s Associate Chair and Director of its graduate programs. External to Georgia Tech, he currently serves as Chair of the SIAM Activity Group on Supercomputing (2018-2020); co-chaired the Technical Papers Program of the “Supercomputing” (SC) Conference in 2016; and serves as an associate editor of the ACM Transactions on Parallel Computing (TOPC), and previously for the International Journal of High-Performance Computing Applications and IEEE Transactions on Parallel and Distributed Systems. He received his Ph.D. in Computer Science from the University of California, Berkeley, and was a postdoctoral scholar in the Center for Advanced Scientific Computing the Lawrence Livermore National Laboratory.

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