A study and power-performance evaluation of an on-chip memory processor with an arithmetic acceleration mechanism
A study and power-performance evaluation of an on-chip memory processor with an arithmetic acceleration mechanism
高橋 睦史, 佐藤 三久, 高橋 大介, 朴 泰祐, 宇川 彰, 中村 宏, 青木 秀貴, 澤本 英雄, 助川直伸: A study and power-performance evaluation of an on-chip memory processor with an arithmetic acceleration mechanism, Proc. 2008 Symposium on High Performance Computing and Computational Science (HPCS 2008), pp. 33-40, (2008). (in Japanese)
Proc. Symposium on High Performance Computing and Computational Science (HPCS 2008)
BiBTeX entry
@inproceedings{hpcs2008-15539,
title = {演算加速機構を持つオンチップメモリプロセッサの検討と電力性能評価},
booktitle = {ハイパフォーマンスコンピューティングと計算科学シンポジウム HPCS2008論文集},
pages = {33-40},
year = {2008},
}